[
  {
    "Mnemonic": "ADC",
    "Mode": "M3",
    "Operands": "Rd, Rr",
    "Example": "adc r3, r1",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Add with Carry two Registers",
    "Operation": "Rd <- Rd + Rr + C",
    "Flags": "Z,C,N,V,H",
    "Bits": "0001 11rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "ADD",
    "Mode": "M3",
    "Operands": "Rd, Rr",
    "Example": "add r0,r2",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Add two Registers",
    "Operation": "Rd <- Rd + Rr",
    "Flags": "Z,C,N,V,H",
    "Bits": "0000 11rd dddd rrrr",
    "Clocks": "1"
  },
    {
    "Mnemonic": "ADIW",
    "Operands": "Rdl,K",
    "Example": "adiw r25:24, 1",
    "Restrictions": "d in {24,26,28,30}, 0<=K<=63",
    "Description": "Add Immediate to Word",
    "Operation": "Rdh:Rdl <- Rdh:Rdl + K",
    "Flags": "Z,C,N,V,S",
    "Bits": "1001 0110 KKdd KKKK",
    "Clocks": "2"
  },
  {
    "Mnemonic": "SUB",
    "Mode": "M3",
    "Operands": "Rd, Rr",
    "Example": "sub r2, r1",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Subtract two Registers",
    "Operation": "Rd <- Rd - Rr",
    "Flags": "Z,C,N,V,H",
    "Bits": "0001 10rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SUBI",
    "Operands": "Rd, K",
    "Example": "subi r12, 128",
    "Restrictions": "0<=d<=31, 0<=K<=255",
    "Description": "Subtract Constant from Register",
    "Operation": "Rd <- Rd - K",
    "Flags": "Z,C,N,V,H",
    "Bits": "0101 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SBC",
    "Mode": "M3",
    "Operands": "Rd, Rr",
    "Example": "subc r3, r4",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Subtract with Carry two Registers",
    "Operation": "Rd <- Rd - Rr - C",
    "Flags": "Z,C,N,V,H",
    "Bits": "0000 10rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SBCI",
    "Operands": "Rd, K",
    "Example": "sbci r27, 128",
    "Restrictions": "16<=d<=31, 0<=K<=255",
    "Description": "Subtract with Carry Constant from Reg.",
    "Operation": "Rd <- Rd - K - C",
    "Flags": "Z,C,N,V,H",
    "Bits": "0100 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SBIW",
    "Operands": "Rdl,K",
    "Example": "sbiw r24, 57",
    "Restrictions": "d in {24,26,28,30}, 0<=K<=63",
    "Description": "Subtract Immediate from Word",
    "Operation": "Rdh:Rdl <- Rdh:Rdl - K",
    "Flags": "Z,C,N,V,S",
    "Bits": "1001 0111 KKdd KKKK",
    "Clocks": "2"
  },
  {
    "Mnemonic": "AND",
    "Mode": "M3",
    "Operands": "Rd, Rr",
    "Example": "and r2, r3",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Logical AND Registers",
    "Operation": "Rd <- Rd & Rr",
    "Flags": "Z,N,V",
    "Bits": "0010 00rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "ANDI",
    "Operands": "Rd, K",
    "Example": "andi r17, 0x0f",
    "Restrictions": "16<=d<=31, 0<=K<=255",
    "Description": "Logical AND Register and Constant",
    "Operation": "Rd <- Rd & K",
    "Flags": "Z,N,V",
    "Bits": "0111 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "OR",
    "Mode": "2",
    "Operands": "Rd, Rr",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<-r<-31",
    "Description": "Logical OR Registers",
    "Operation": "Rd <- Rd | Rr",
    "Flags": "Z,N,V",
    "Bits": "0010 10rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "ORI",
    "Operands": "Rd, K",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=K<=255",
    "Description": "Logical OR Register and Constant",
    "Operation": "Rd <- Rd | K",
    "Flags": "Z,N,V",
    "Bits": "0110 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "EOR",
    "Mode": "M3",
    "Operands": "Rd, Rr",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Exclusive OR Registers",
    "Operation": "Rd <- Rd ^ Rr",
    "Flags": "Z,N,V",
    "Bits": "0010 01rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "COM",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "One’s Complement",
    "Operation": "Rd <- 0xFF - Rd",
    "Flags": "Z,C,N,V",
    "Bits": "1001 010d dddd 0000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "NEG",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Two’s Complement",
    "Operation": "Rd  0x00  Rd",
    "Flags": "Z,C,N,V,H",
    "Bits": "1001 010d dddd 0001",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SBR",
    "Operands": "Rd,K",
    "Example": "",
    "Restrictions": "16<=d<=31, 0<=K<=255",
    "Description": "Set Bit(s) in Register",
    "Operation": "Rd <- Rd v K",
    "Flags": "Z,N,V",
    "Bits": "0110 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CBR",
    "Operands": "Rd,K",
    "Example": "",
    "Restrictions": "16<=d<=31, 0<=k<=255",
    "Description": "Clear Bit(s) in Register",
    "Operation": "Rd <- Rd & (0xFF - K)",
    "Flags": "Z,N,V",
    "Bits": "0111 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "INC",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Increment",
    "Operation": "Rd <- Rd + 1",
    "Flags": "Z,N,V",
    "Bits": "1001 010d dddd 0011",
    "Clocks": "1"
  },
  {
    "Mnemonic": "DEC",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Decrement",
    "Operation": "Rd <- Rd - 1",
    "Flags": "Z,N,V",
    "Bits": "1001 010d dddd 1010",
    "Clocks": "1"
  },
  {
    "Mnemonic": "TST",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Test for Zero or Minus",
    "Operation": "Rd <- Rd - Rd",
    "Flags": "Z,N,V",
    "Bits": "0010 00dd dddd dddd",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SER",
    "Operands": "Rd",
    "Example": "",
    "Description": "Set Register",
    "Operation": "Rd <- 0xFF",
    "Flags": "None",
    "Bits": "1110 1111 dddd 1111",
    "Clocks": "1"
  },
  {
    "Mnemonic": "RJMP",
    "Operands": "k",
    "Example": "",
    "Operands": "-2048<=k<=2048",
    "Description": "Relative Jump",
    "Operation": "PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1100 kkkk kkkk kkkk",
    "Clocks": "2"
  },
  {
    "Mnemonic": "IJMP",
    "Description": "Indirect Jump to (Z)",
    "Example": "",
    "Operation": "PC <- [Z]",
    "Flags": "None",
    "Bits": "1001 0100 0000 1001",
    "Clocks": "2"
  },
  {
    "Mnemonic": "RCALL",
    "Operands": "k",
    "Example": "",
    "Operands": "-2048<=k<=2048",
    "Description": "Relative Subroutine Call",
    "Operation": "PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1101 kkkk kkkk kkkk",
    "Clocks": "3"
  },
  {
    "Mnemonic": "ICALL",
    "Description": "Indirect Call to (Z)",
    "Example": "",
    "Operation": "PC <- [Z]",
    "Flags": "None",
    "Bits": "1001 0101 0000 1001",
    "Clocks": "3"
  },
  {
    "Mnemonic": "RET",
    "Description": "Subroutine Return",
    "Example": "",
    "Operation": "PC <- [SP]. SP <- SP + 2]",
    "Flags": "None",
    "Bits": "1001 0101 0000 1000",
    "Clocks": "4"
  },
  {
    "Mnemonic": "RETI",
    "Description": "Interrupt Return",
    "Example": "",
    "Operation": "PC <- [SP], SP <- SP -2",
    "Flags": "I",
    "Bits": "1001 0101 0001 1000",
    "Clocks": "4"
  },
  {
    "Mnemonic": "CPSE",
    "Mode": "M3",
    "Operands": "Rd,Rr",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Compare, Skip if Equal",
    "Operation": "if (Rd = Rr) PC <- PC + 2 or 3",
    "Flags": "None",
    "Bits": "0001 00rd dddd rrrr",
    "Clocks": "1/2/3"
  },
  {
    "Mnemonic": "CP",
    "Mode": "M2",
    "Operands": "Rd,Rr",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Compare",
    "Operation": "Rd - Rr",
    "Flags": "Z, N,V,C,H",
    "Bits": "0001 01rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CPC",
    "Mode": "M3",
    "Operands": "Rd,Rr",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=r<=31",
    "Description": "Compare with Carry",
    "Operation": "Rd - Rr C",
    "Flags": "Z, N,V,C,H",
    "Bits": "0000 00rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CPI",
    "Operands": "Rd,K",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=K<=255",
    "Description": "Compare Register with Immediate",
    "Operation": "Rd  K",
    "Flags": "Z, N,V,C,H",
    "Bits": "0011 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SBRC",
    "Mode": "M2",
    "Operands": "Rr, b",
    "Example": "",
    "Restrictions": "0<=r<=31, 0<=b<=7",
    "Description": "Skip if Bit in Register Cleared",
    "Operation": "if (Rr(b)=0) PC <- PC + 2 or 3",
    "Flags": "None",
    "Bits": "1111 110r rrrr 0bbb",
    "Clocks": "1/2/3"
  },
  {
    "Mnemonic": "SBRS",
    "Mode": "M2",
    "Operands": "Rr, b",
    "Example": "",
    "Restrictions": "0<=r<=31, 0<=b<=7",
    "Description": "Skip if Bit in Register is Set",
    "Operation": "if (Rr(b)=1) PC <- PC + 2 or 3",
    "Flags": "None",
    "Bits": "1111 111r rrrr 0bbb",
    "Clocks": "1/2/3"
  },
  {
    "Mnemonic": "SBIC",
    "Operands": "A, b",
    "Example": "",
    "Restrictions": "0<=A<=31, 0<=b<=7",
    "Description": "Skip if Bit in I/O Register Cleared",
    "Operation": "if (P(b)=0) PC <- PC + 2 or 3",
    "Flags": "None",
    "Bits": "1001 1001 AAAA Abbb",
    "Clocks": "1/2/3"
  },
  {
    "Mnemonic": "SBIS",
    "Operands": "A, b",
    "Example": "",
    "Restrictions": "0<=A<=31, 0<=b<=7",
    "Description": "Skip if Bit in I/O Register is Set",
    "Operation": "if (P(b)=1) PC <- PC + 2 or 3",
    "Flags": "None",
    "Bits": "1001 1011 AAAA Abbb",
    "Clocks": "1/2/3"
  },
  {
    "Mnemonic": "BRBS",
    "Operands": "s, k",
    "Example": "",
    "Restrictions": "0<=s<=7, -64<=k<=63",
    "Description": "Branch if Status Flag Set",
    "Operation": "if (SREG(s) = 1) then PC <- PC+k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk ksss",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRBC",
    "Operands": "s, k",
    "Example": "",
    "Restrictions": "0<=s<=7, -64<=k<=63",
    "Description": "Branch if Status Flag Cleared",
    "Operation": "if (SREG(s) = 0) then PC <- PC+k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk ksss",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BREQ",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Equal",
    "Operation": "if (Z = 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k001",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRNE",
    "Operands": "k",
    "Example": "",
    "Description": "Branch if Not Equal",
    "Operation": "if (Z = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k001",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRCS",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Carry Set",
    "Operation": "if (C = 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k000",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRCC",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Carry Cleared",
    "Operation": "if (C = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k000",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRSH",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Same or Higher",
    "Operation": "if (C = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k000",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRLO",
    "Operands": "k",
    "Example": "",
    "Description": "Branch if Lower",
    "Operation": "if (C = 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k000",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRMI",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Minus",
    "Operation": "if (N = 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k010",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRPL",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Plus",
    "Operation": "if (N = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k010",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRGE",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Greater or Equal, Signed",
    "Operation": "if (N  V= 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k100",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRLT",
    "Operands": "k",
    "Example": "",
    "Description": "Branch if Less Than Zero, Signed",
    "Operation": "if (N  V= 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k100",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRHS",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Half Carry Flag Set",
    "Operation": "if (H = 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k101",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRHC",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Half Carry Flag Cleared",
    "Operation": "if (H = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k101",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRTS",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if T Flag Set",
    "Operation": "if(T=1)then PC<- C+k +1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k110",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRTC",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if T Flag Cleared",
    "Operation": "if (T = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k110",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRVS",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Overflow Flag is Set",
    "Operation": "if (V = 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k011",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRVC",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Overflow Flag is Cleared",
    "Operation": "if (V = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k011",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRIE",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Interrupt Enabled",
    "Operation": "if ( I = 1) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 00kk kkkk k111",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "BRID",
    "Operands": "k",
    "Example": "",
    "Restrictions": "-64<=k<=63",
    "Description": "Branch if Interrupt Disabled",
    "Operation": "if ( I = 0) then PC <- PC + k + 1",
    "Flags": "None",
    "Bits": "1111 01kk kkkk k111",
    "Clocks": "1/2"
  },
  {
    "Mnemonic": "SBI",
    "Operands": "A,b",
    "Example": "",
    "Restrictions": "0<=A<=31, 0<=b<=7",
    "Description": "Set Bit in I/O Register",
    "Operation": "I/O(P,b) <- 1",
    "Flags": "None",
    "Bits": "1001 1010 AAAA Abbb",
    "Clocks": "2"
  },
  {
    "Mnemonic": "CBI",
    "Operands": "A,b",
    "Example": "",
    "Restrictions": "0<=A<=31, 0<=b<=7",
    "Description": "Clear Bit in I/O Register",
    "Operation": "I/O(P,b) <- 0",
    "Flags": "None",
    "Bits": "1001 1000 AAAA Abbb",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LSL",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Logical Shift Left",
    "Operation": "Rd(n+1) <- Rd(n), Rd(0) <- 0",
    "Flags": "Z,C,N,V",
    "Bits": "0000 11dd dddd dddd",
    "Clocks": "1"
  },
  {
    "Mnemonic": "LSR",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Logical Shift Right",
    "Operation": "Rd(n) <- Rd(n+1), Rd(7) <- 0",
    "Flags": "Z,C,N,V",
    "Bits": "1001 010d dddd 0110",
    "Clocks": "1"
  },
  {
    "Mnemonic": "ROL",
    "Operands": "Rd",
    "Example": "",
    "Description": "Rotate Left Through Carry",
    "Restrictions": "0<=d<=31",
    "Operation": "Rd(0)C,Rd(n+1)<- Rd(n),C <- Rd(7)",
    "Flags": "Z,C,N,V",
    "Bits": "0001 11dd dddd dddd",
    "Clocks": "1"
  },
  {
    "Mnemonic": "ROR",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Rotate Right Through Carry",
    "Operation": "Rd(7)<- C,Rd(n)<- Rd(n+1),<- Rd(0)",
    "Flags": "Z,C,N,V",
    "Bits": "1001 010d dddd 0111",
    "Clocks": "1"
  },
  {
    "Mnemonic": "ASR",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Arithmetic Shift Right",
    "Operation": "Rd(n) <- Rd(n+1), n=0..6",
    "Flags": "Z,C,N,V",
    "Bits": "1001 010d dddd 0101",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SWAP",
    "Mode": "M1",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Swap Nibbles",
    "Operation": "Rd(3..0<- Rd(7..4),Rd(7..4 <- Rd(3..0)",
    "Flags": "None",
    "Bits": "1001 010d dddd 0010",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SET",
    "Operands": "s",
    "Example": "",
    "Description": "Flag Set",
    "Operation": "SREG(s) <- 1",
    "Flags": "SREG(s)",
    "Bits": "0000 0000 0000 0000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLR",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Clear register",
    "Operation": "Rd <= Rd XOR Rd",
    "Flags": "S,V,N,Z",
    "Bits": "0010 01dd dddd dddd",
    "Clocks": "1"
  },
  {
    "Mnemonic": "BCLR",
    "Operands": "s",
    "Example": "",
    "Restrictions": "0<=s<=7",
    "Description": "Flag Clear",
    "Operation": "SREG(s) <- 0",
    "Flags": "SREG(s)",
    "Bits": "1001 0100 0sss 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "BST",
    "Mode": "M2",
    "Operands": "Rd, b",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=b<=7",
    "Description": "Bit Store from Register to T",
    "Operation": "T <- Rr(b)",
    "Flags": "T",
    "Bits": "1111 101d dddd 0bbb",
    "Clocks": "1"
  },
  {
    "Mnemonic": "BLD",
    "Mode": "M2",
    "Operands": "Rd, b",
    "Example": "",
    "Description": "Bit load from T to Register",
    "Operation": "Rd(b) <- T",
    "Flags": "None",
    "Bits": "1111 100d dddd 0bbb",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SEC",
    "Description": "Set Carry",
    "Example": "",
    "Operation": "C <- 1",
    "Flags": "C",
    "Bits": "1001 0100 0000 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLC",
    "Description": "Clear Carry",
    "Example": "",
    "Operation": "C <- 0",
    "Flags": "C",
    "Bits": "1001 0100 1000 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SEN",
    "Description": "Set Negative Flag",
    "Example": "",
    "Operation": "N <- 1",
    "Flags": "N",
    "Bits": "1001 0100 0010 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLN",
    "Description": "Clear Negative Flag",
    "Example": "",
    "Operation": "N <- 0",
    "Flags": "N",
    "Bits": "1001 0100 1010 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SEZ",
    "Description": "Set Zero Flag",
    "Example": "",
    "Operation": "Z <- 1",
    "Flags": "Z",
    "Bits": "1001 0100 0001 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLZ",
    "Description": "Clear Zero Flag",
    "Example": "",
    "Operation": "Z <- 0",
    "Flags": "Z",
    "Bits": "1001 0100 1001 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SEI",
    "Description": "Global Interrupt Enable",
    "Example": "",
    "Operation": "I <- 1",
    "Flags": "I",
    "Bits": "1001 0100 0111 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLI",
    "Description": "Global Interrupt Disable",
    "Example": "",
    "Operation": "I <- 0",
    "Flags": "I",
    "Bits": "1001 0100 1111 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SES",
    "Description": "Set Signed Test Flag",
    "Example": "",
    "Operation": "S <- 1",
    "Flags": "S",
    "Bits": "1001 0100 0100 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLS",
    "Description": "Clear Signed Test Flag",
    "Example": "",
    "Operation": "S <- 0",
    "Flags": "S",
    "Bits": "1001 0100 1100 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SEV",
    "Description": "Set Twos Complement Overflow.",
    "Example": "",
    "Operation": "V <- 1",
    "Flags": "V",
    "Bits": "1001 0100 0011 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLV",
    "Description": "Clear Twos Complement Overflow",
    "Example": "",
    "Operation": "V <- 0",
    "Flags": "V",
    "Bits": "1001 0100 1011 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SET",
    "Description": "Set T in SREG",
    "Example": "",
    "Operation": "T <- 1",
    "Flags": "T",
    "Bits": "1001 0100 0110 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLT",
    "Description": "Clear T in SREG",
    "Example": "",
    "Operation": "T <- 0",
    "Flags": "T",
    "Bits": "1001 0100 1110 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SEH",
    "Description": "Set Half Carry Flag in SREG",
    "Example": "",
    "Operation": "H <- 1",
    "Flags": "H",
    "Bits": "1001 0100 0101 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "CLH",
    "Description": "Clear Half Carry Flag in SREG",
    "Example": "",
    "Operation": "H <- 0",
    "Flags": "H",
    "Bits": "1001 0100 1101 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "MOV",
    "Mode": "2",
    "Operands": "Rd, Rr",
    "Example": "",
    "Restrictions": "0<=d<=31, -<=r<=31",
    "Description": "Move Between Registers",
    "Operation": "Rd <- Rr",
    "Flags": "None",
    "Bits": "0010 11rd dddd rrrr",
    "Clocks": "1"
  },
  {
    "Mnemonic": "MOVW",
    "Mode": "14",
    "Operands": "Rd, Rr",
    "Example": "",
    "Restrictions": "r in even, d in even",
    "Description": "Copy Register Word",
    "Operation": "Rd+1:Rd <- Rr+1:Rr",
    "Flags": "None",
    "Bits": "0000 0001 dddd rrrr",
     "Clocks": "1"
  },
  {
    "Mnemonic": "LDI",
    "Operands": "Rd, K",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=K<=255",
    "Description": "Load Immediate",
    "Operation": "Rd <- K",
    "Flags": "None",
    "Bits": "1110 KKKK dddd KKKK",
    "Clocks": "1"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, X",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect",
    "Operation": "Rd <- (X)",
    "Flags": "None",
    "Bits": "1001 000d dddd 1100",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, X+",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect and Post-Inc.",
    "Operation": "Rd <-  (X), X <-  X + 1",
    "Flags": "None",
    "Bits": "1001 000d dddd 1101",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, -X",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect and Pre-Dec.",
    "Operation": "X <- X - 1, Rd <- (X)",
    "Flags": "None",
    "Bits": "1001 000d dddd 1110",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, Y",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect",
    "Operation": "Rd <-  (Y)",
    "Flags": "None",
    "Bits": "1000 000d dddd 1000",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, Y+",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect and Post-Inc.",
    "Operation": "Rd <- (Y), Y <- Y + 1",
    "Flags": "None",
    "Bits": "1001 000d dddd 1001",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, -Y",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect and Pre-Dec.",
    "Operation": "Y <- Y - 1, Rd <- (Y)",
    "Flags": "None",
    "Bits": "1001 000d dddd 1010",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LDD",
    "Operands": "Rd,Y+q",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=q<=63",
    "Description": "Load Indirect with Displacement",
    "Operation": "Rd <- (Y + q)",
    "Flags": "None",
    "Bits": "10q0 qq0d dddd 1qqq",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, Z",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect",
    "Operation": "Rd <- (Z)",
    "Flags": "None",
    "Bits": "1000 000d dddd 0000",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, Z+",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect and Post-Inc.",
    "Operation": "Rd <- (Z), Z <- Z+1",
    "Flags": "None",
    "Bits": "1001 000d dddd 0001",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LD",
    "Operands": "Rd, -Z",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Load Indirect and Pre-Dec.",
    "Operation": "Z <- Z - 1, Rd <- (Z)",
    "Flags": "None",
    "Bits": "1001 000d dddd 0010",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LDD",
    "Operands": "Rd, Z+q",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=q<=63",
    "Description": "Load Indirect with Displacement",
    "Operation": "Rd <- (Z + q)",
    "Flags": "None",
    "Bits": "10q0 qq0d dddd 0qqq",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LDS",
    "Operands": "Rd, k",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=k<=65535",
    "Description": "Load Direct from SRAM",
    "Operation": "Rd <- (k)",
    "Flags": "None",
    "Bits": "1001 000d dddd 0000 kkkk kkkk kkkk kkkk",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "X, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect",
    "Operation": "(X) <- Rr",
    "Flags": "None",
    "Bits": "1001 001r rrrr 1100",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "X+, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect and Post-Inc.",
    "Operation": "(X) <- Rr, X <- X + 1",
    "Flags": "None",
    "Bits": "1001 001r rrrr 1101",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "-X, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect and Pre-Dec.",
    "Operation": "X <- X - 1, (X) <- Rr",
    "Flags": "None",
    "Bits": "1001 001r rrrr 1110",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "Y, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect",
    "Operation": "(Y) <- Rr",
    "Flags": "None",
    "Bits": "1000 001r rrrr 1000",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "Y+, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect and Post-Inc.",
    "Operation": "(Y) <- Rr, Y <- Y + 1",
    "Flags": "None",
    "Bits": "1001 001r rrrr 1001",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "- Y, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect and Pre-Dec.",
    "Operation": "Y <- Y - 1, (Y) <- Rr",
    "Flags": "None",
    "Bits": "1001 001r rrrr 1010",
    "Clocks": "2"
  },
  {
    "Mnemonic": "STD",
    "Operands": "Y+q,Rr",
    "Example": "",
    "Restrictions": "0<=r<=31, 0<=q<=63",
    "Description": "Store Indirect with Displacement",
    "Operation": "(Y + q) <-  Rr",
    "Flags": "None",
    "Bits": "10q0 qq1r rrrr `qqq",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "Z, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect",
    "Operation": "(Z) <- Rr",
    "Flags": "None",
    "Bits": "1000 001r rrrr 0000",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "Z+, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect and Post-Inc.",
    "Operation": "(Z) <- Rr, Z <- Z + 1",
    "Flags": "None",
    "Bits": "1001 001r rrrr 0001",
    "Clocks": "2"
  },
  {
    "Mnemonic": "ST",
    "Operands": "-Z, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Store Indirect and Pre-Dec.",
    "Operation": "Z <- Z - 1, (Z) <- Rr",
    "Flags": "None",
    "Bits": "1001 001r rrrr 0010",
    "Clocks": "2"
  },
  {
    "Mnemonic": "STD",
    "Operands": "Z+q,Rr",
    "Example": "",
    "Restrictions": "0<=r<=31, 0<=q<=63",
    "Description": "Store Indirect with Displacement",
    "Operation": "(Z + q) <- Rr",
    "Flags": "None",
    "Bits": "10q0 qq1r rrrr 0qqq",
    "Clocks": "2"
  },
  {
    "Mnemonic": "STS",
    "Operands": "k, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31, 0<=k<=65535",
    "Description": "Store Direct to SRAM",
    "Operation": "(k) <- Rr",
    "Flags": "None",
    "Bits": "1001 001r rrrr 0000 kkkk kkkk kkkk kkkk",
    "Clocks": "2"
  },
  {
    "Mnemonic": "LPM",
    "Description": "Load Program Memory",
    "Example": "",
    "Operation": "R0 <- (Z)",
    "Flags": "None",
    "Bits": "1001 0101 1100 1000",
    "Clocks": "3"
  },
  {
    "Mnemonic": "LPM",
    "Operands": "Rd, Z",
    "Example": "",
    "Restrictions": "0<-d<=31",
    "Description": "Load Program Memory",
    "Operation": "Rd <- (Z)",
    "Flags": "None",
    "Bits": "1001 000d dddd 0100",
    "Clocks": "3"
  },
  {
    "Mnemonic": "LPM",
    "Operands": "Rd, Z+",
    "Example": "",
    "Description": "Load Program Memory and Post-Inc",
    "Operation": "Rd <- (Z), Z <- Z+1",
    "Flags": "None",
    "Bits": "1001 000d dddd 0101",
    "Clocks": "3"
  },
  {
    "Mnemonic": "SPM",
    "Description": "Store Program Memory",
    "Example": "",
    "Operation": "(z) <- R1:R0",
    "Flags": "None",
    "Bits": "1001 0101 1110 1000",
    "Clocks": ""
  },
  {
    "Mnemonic": "IN",
    "Mode": "4",
    "Operands": "Rd, A",
    "Example": "",
    "Restrictions": "0<=d<=31, 0<=A<=63",
    "Description": "In Port",
    "Operation": "Rd <- P",
    "Flags": "None",
    "Bits": "1011 0AAd dddd AAAA",
    "Clocks": ""
  },
  {
    "Mnemonic": "OUT",
    "Mode": "4",
    "Operands": "A, Rr",
    "Example": "",
    "Restrictions": "0<=r<=31, 0<=A<=63",
    "Description": "Out Port",
    "Operation": "P <- Rr",
    "Flags": "None",
    "Bits": "1011 1AAr rrrr AAAA",
    "Clocks": ""
  },
  {
    "Mnemonic": "PUSH",
    "Operands": "Rr",
    "Example": "",
    "Restrictions": "0<=r<=31",
    "Description": "Push Register on Stack",
    "Operation": "[SP] <- Rr, SP <- SP - 1",
    "Flags": "None",
    "Bits": "1001 001r rrrr 1111",
    "Clocks": ""
  },
  {
    "Mnemonic": "POP",
    "Operands": "Rd",
    "Example": "",
    "Restrictions": "0<=d<=31",
    "Description": "Pop Register from Stack",
    "Operation": "Rd <- [SP], SP <- SP + 1",
    "Flags": "None",
    "Bits": "1001 000d dddd 1111",
    "Clocks": "2"
  },
  {
    "Mnemonic": "NOP",
    "Description": "No Operation",
    "Example": "",
    "Flags": "None",
    "Bits": "0000 0000 0000 0000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "SLEEP",
    "Description": "Sleep",
    "Example": "",
    "Flags": "None",
    "Bits": "1001 0101 1000 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "WDR",
    "Description": "Watchdog Reset",
    "Example": "",
    "Flags": "None",
    "Bits": "1001 0101 1010 1000",
    "Clocks": "1"
  },
  {
    "Mnemonic": "BREAK",
    "Description": "Break",
    "Example": "",
    "Flags": "None",
    "Bits": "1001 0101 1001 1000"
  }
]